1. Technical Field
The disclosure relates generally to integrated circuit (IC) chip testing, and more particularly, to a method and system of identifying sequential functional paths for IC testing.
2. Background Art
Integrated circuit (IC) chips are tested prior to being released for sale to ensure that they operate correctly. Conventionally, transition fault test patterns are generated using the easiest and shortest paths through combinational logic possible. Each transition fault test pattern attempts to test for faults by testing the delay at one internal node within the circuit. Many longer and more critical paths exist that may not be tested by these transition fault test patterns. These untested paths may fail at the customer in functional operation leading to unacceptably high failure rates. However, testing the infinite number of longer paths is currently impossible due to test time and test generation effort constraints. In addition, a number of these longer paths are false paths that do not need to be tested. For example, certain (Boolean false) paths will never be used during functional operation or testing of the circuit, and do not need to be considered during testing. In addition, in another example, certain (functionally false) paths are never used during functional operation of the IC, but may be sensitized during testing. As a result, a test resulting in a fault detection of a functionally false path may lead to unnecessarily rejecting good products.